Invention Grant
- Patent Title: Dishing prevention columns for bipolar junction transistors
-
Application No.: US15935363Application Date: 2018-03-26
-
Publication No.: US10510685B2Publication Date: 2019-12-17
- Inventor: Yi-Huan Chen , Chien-Chih Chou , Kong-Beng Thei , Meng-Han Lin
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L29/735 ; H01L21/3105 ; H01L29/66 ; H01L29/08 ; H01L29/06 ; H01L29/10

Abstract:
In some embodiments, a bipolar junction transistor (BJT) is provided. The BJT may include a collector region that is disposed within a semiconductor substrate. A base region that is disposed within the semiconductor substrate and arranged within the collector region. An emitter region that is disposed within the semiconductor substrate and arranged within the base region. A pre-metal dielectric layer that is disposed over an upper surface of the semiconductor substrate and that separates the upper surface of the semiconductor substrate from a lowermost metal interconnect layer. A first plurality of dishing prevention columns that are arranged over the emitter region and within the pre-metal dielectric layer, where the plurality of dishing prevention columns each include a dummy gate that is conductive and electrically floating.
Public/Granted literature
- US20190103367A1 DISHING PREVENTION COLUMNS FOR BIPOLAR JUNCTION TRANSISTORS Public/Granted day:2019-04-04
Information query
IPC分类: