Invention Grant
- Patent Title: Metastable true random number generator realized on FPGA
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Application No.: US16045688Application Date: 2018-07-25
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Publication No.: US10514894B2Publication Date: 2019-12-24
- Inventor: Pengjun Wang , Hongzhen Fang , Yuejun Zhang
- Applicant: Ningbo University
- Applicant Address: CN Zhejiang
- Assignee: Ningbo University
- Current Assignee: Ningbo University
- Current Assignee Address: CN Zhejiang
- Agency: JCIPRNET
- Priority: CN201711141886 20171117
- Main IPC: G06F7/58
- IPC: G06F7/58 ; H03K3/84

Abstract:
A metastable true random number generator realized on an FPGA comprises a configurable delay chain including rough adjustment module and a fine adjustment module. The rough adjustment module comprises 32 rough adjustment cells each including a 1st 6-input lookup table and a two-to-one selector. The 1st input port of each 1st 6-input lookup table is connected to the 1st input terminal of the corresponding two-to-one selector, and the connecting terminal is the input terminal of the corresponding rough adjustment cell. The 2nd input port, the 3rd input port, the 4th input port, the 5th input port and the 6th input port of each 1st 6-input lookup table are all accessed to a low level 0. The output port of each 1st 6-input lookup table is connected to the 2nd input terminal of the corresponding two-to-one selector. The metastable true random number generator has the advantages of being capable of well counteracting inherent delay deviations, high in automation degree and high in output rate and having an operating point not prone to deviation.
Public/Granted literature
- US20190155576A1 METASTABLE TRUE RANDOM NUMBER GENERATOR REALIZED ON FPGA Public/Granted day:2019-05-23
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