Invention Grant
- Patent Title: Merged pillar structures and method of generating layout diagram of same
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Application No.: US15882188Application Date: 2018-01-29
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Publication No.: US10515178B2Publication Date: 2019-12-24
- Inventor: Hiranmay Biswas , Chung-Hsing Wang , Kuo-Nan Yang , Yi-Kan Cheng
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Hauptman Ham, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H01L27/02 ; H01L27/118

Abstract:
A method (of generating a layout diagram of a conductive line structure includes: determining that a first set of first to fourth short pillar patterns (which represent portions of an M(i) layer of metallization and are located relative to a grid), violates a minimum transverse-routing (TVR) distance of alpha-direction-separation, wherein (1) the grid has orthogonal alpha and beta tracks, and (2) the short pillar patterns have long axes which are substantially co-track aligned with a first one of the alpha tracks and have a first distance (of alpha-direction-separation between immediately adjacent members of the first set) which is less than the TVR distance; and merging pairings of the first & second and third & fourth short pillar patterns into corresponding first and second medium pillar patterns which have a second distance of alpha-direction-separation therebetween; the second value being greater than the TVR distance.
Public/Granted literature
- US20190065653A1 MERGED PILLAR STRUCTURES AND METHOD OF GENERATING LAYOUT DIAGRAM OF SAME Public/Granted day:2019-02-28
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