Invention Grant
- Patent Title: Integrated circuit and method of generating integrated circuit layout
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Application No.: US16122762Application Date: 2018-09-05
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Publication No.: US10515944B2Publication Date: 2019-12-24
- Inventor: Fong-Yuan Chang , Kuo-Nan Yang , Chung-Hsing Wang , Lee-Chung Lu , Sheng-Fong Chen , Po-Hsiang Huang , Hiranmay Biswas , Sheng-Hsiung Chen , Aftab Alam Khan
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Maschoff Brennan
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L27/02 ; H01L23/522 ; G06F17/50 ; H01L27/118

Abstract:
An integrated circuit includes a cell layer, a first metal layer, and a first conductive via. The cell layer includes first and second cells, each of which is configured to perform a circuit function. The first metal layer is above the cell layer and includes a first conductive feature that extends from the first cell into the second cell and that is configured to receive a supply voltage. A first conductive via interconnects the cell layer and the metal layer.
Public/Granted literature
- US20190148352A1 INTEGRATED CIRCUIT AND METHOD OF GENERATING INTEGRATED CIRCUIT LAYOUT Public/Granted day:2019-05-16
Information query
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