Invention Grant
- Patent Title: Phase-locked loop and delay-locked loop
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Application No.: US16181625Application Date: 2018-11-06
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Publication No.: US10516400B2Publication Date: 2019-12-24
- Inventor: Hyung Ki Huh , Dong Joon Lee
- Applicant: Anapass Inc.
- Applicant Address: KR Seoul
- Assignee: Anapass Inc.
- Current Assignee: Anapass Inc.
- Current Assignee Address: KR Seoul
- Agency: Paratus Law Group, PLLC
- Priority: KR10-2017-0159536 20171127
- Main IPC: H03L7/06
- IPC: H03L7/06 ; H03L7/08 ; H03L7/099 ; H03L7/081 ; H03L7/091 ; H03L7/087

Abstract:
Disclosed is a phase-locked loop and a delay-locked loop. When the phase-locked loop switches from a sleep state to an active state, a frequency of a reference signal is the same as a frequency of a reference signal which has been synchronized in a previous active state. The phase-locked loop alternately operates in a sleep state and an active state. A frequency-divided output signal of the phase-locked loop is synchronized with a frequency-divided reference signal, when the phase-locked loop switches from a sleep state to an active state, a frequency of the frequency-divided output signal is identical to a frequency of a frequency-divided output signal which has been synchronized in a previous active state. Information corresponding to the frequency of the frequency-divided output signal which has been synchronized in the previous active state is stored in a capacitor.
Public/Granted literature
- US20190165792A1 PHASE-LOCKED LOOP AND DELAY-LOCKED LOOP Public/Granted day:2019-05-30
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