Phase-locked loop and delay-locked loop
Abstract:
Disclosed is a phase-locked loop and a delay-locked loop. When the phase-locked loop switches from a sleep state to an active state, a frequency of a reference signal is the same as a frequency of a reference signal which has been synchronized in a previous active state. The phase-locked loop alternately operates in a sleep state and an active state. A frequency-divided output signal of the phase-locked loop is synchronized with a frequency-divided reference signal, when the phase-locked loop switches from a sleep state to an active state, a frequency of the frequency-divided output signal is identical to a frequency of a frequency-divided output signal which has been synchronized in a previous active state. Information corresponding to the frequency of the frequency-divided output signal which has been synchronized in the previous active state is stored in a capacitor.
Public/Granted literature
Information query
Patent Agency Ranking
0/0