Invention Grant
- Patent Title: Package assembly for embedded die and associated techniques and configurations
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Application No.: US16380529Application Date: 2019-04-10
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Publication No.: US10522483B2Publication Date: 2019-12-31
- Inventor: Takashi Shuto
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L25/11
- IPC: H01L25/11 ; H01L23/31 ; H01L23/00 ; H01L25/18 ; H01L25/00 ; H01L21/56

Abstract:
Embodiments of the present disclosure are directed towards a package assembly for embedded die and associated techniques and configurations. In one embodiment, an apparatus includes a package assembly comprising a die attach layer, a die coupled with the die attach layer, the die having an active side including active devices of the die and an inactive side disposed opposite to the active side, a reinforced plate coupled with the die attach layer, the reinforced plate having a first side and a second side disposed opposite to the first side and a cavity disposed in the reinforced plate and one or more build-up layers coupled with the second side of the reinforced plate, the one or more build-up layers including an insulator and conductive features disposed in the insulator, the conductive features being electrically coupled with the die, wherein the inactive side of the die is in direct contact with the die attach layer, the first side of the reinforced plate is in direct contact with the die attach layer and the die is disposed in the cavity. Other embodiments may be described and/or claimed.
Public/Granted literature
- US20190237413A1 PACKAGE ASSEMBLY FOR EMBEDDED DIE AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS Public/Granted day:2019-08-01
Information query
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