Invention Grant
- Patent Title: Liner layer for dielectric block layer
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Application No.: US15480074Application Date: 2017-04-05
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Publication No.: US10522754B2Publication Date: 2019-12-31
- Inventor: Sundar Narayanan , Zhen Gu , Natividad Vasquez
- Applicant: Crossbar, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Crossbar, Inc.
- Current Assignee: Crossbar, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Wegman Hessler
- Main IPC: H01L45/00
- IPC: H01L45/00

Abstract:
Two-terminal memory devices can be formed in part within a dielectric material that is electrically insulating and operates as a blocking layer to mitigate diffusion of metal particles employed in integrated circuit fabrication. This dielectric material can be protected from other fabrication processes corrosive to the dielectric material (e.g., CMP, HF clean, etc) by a silicon containing liner. Use of the silicon containing liner can enable a minimum thickness of the dielectric material to be preserved and can facilitate step height differences between adjacent material surfaces that form a two-terminal memory device to be on the order of less than about five angstroms. This small step height difference, particularly when underlying a switching layer of the two-terminal memory device, can yield excellent switching characteristics.
Public/Granted literature
- US20170365780A1 LINER LAYER FOR DIELECTRIC BLOCK LAYER Public/Granted day:2017-12-21
Information query
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