A semiconductor apparatus may include a synchronization circuit, and a phase detection circuit. The synchronization circuit may be configured to, based on an operation mode of the semiconductor apparatus, divide a first clock signal to generate first and second divided clock signals or divide a phase-locked clock signal to generate first and second divided clock signals. The phase detection circuit may be configured to use, based on the operation mode of the semiconductor apparatus, either the first and second clock signals created from dividing the first clock signal or the first and second clock signals created from dividing the phase-locked clock signal, to compare either the first divided clock signal or the second divided clock signal with a second clock signal to generate a phase detection signal.