An emulator emulating a DUT emulates a clock generator for generating clock signals of the DUT with jitter. As part of generating clock signals, the emulator generates a jitter clock value for each clock signal. To generate a jitter clock value for a clock signal, the emulator identifies a clock parameter stored for the clock signal and sums the clock parameter with a jitter value randomly selected from the jitter range of the clock signal. When a system fast clock cycle starts, the emulator determines the lowest value from the generated jitter clock values. The emulator outputs an edge on clock signal having the lowest jitter clock value. The emulator generates a new jitter clock value for each clock signal and the process repeats during the next system fast clock cycle.