Memory control circuit with distributed architecture
Abstract:
Disclosed is a device including a distributed controller and a common controller. The distributed controller includes a first circuit to generate an output voltage according to a control signal. The common controller includes a common feedback loop coupled to the distributed controller. The common feedback loop includes an amplifier circuit to generate the control signal, and a second circuit coupled to the amplifier circuit. The second circuit replicates the first circuit and stabilizes the control signal.
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