A system may include a first semiconductor apparatus and a second semiconductor apparatus. Each of the first and second semiconductor apparatuses may receive reference data and a first clock signal. The first semiconductor apparatus may generate a first internal clock signal from the first clock signal, and may output the reference data as transmission data based on the first internal clock signal. The second semiconductor apparatus may generate a second internal clock signal from the first clock signal, and may receive the transmission data based on the second internal clock signal. The second semiconductor apparatus may generate an error detection signal based on the received data and the reference data.