A technique for interconnecting chips by using an interconnection substrate is disclosed. The interconnection substrate includes a base substrate, a first group of electrodes on the base substrate for a first chip to be mounted, and a second group of electrodes on the base substrate for a second chip to be mounted. The interconnection substrate further includes an interconnection layer that includes a first set of pads for the first chip, a second set of pads for the second chip, traces and an organic insulating material. The interconnection layer is disposed on the base substrate and located within a defined area on the base substrate between the first group of electrodes and the second group of the electrodes.