Invention Grant
- Patent Title: Switching circuit capable of reducing parasitic capacitance variation
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Application No.: US16002502Application Date: 2018-06-07
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Publication No.: US10530358B2Publication Date: 2020-01-07
- Inventor: Cheng-Pang Chan , Liang-Huan Lei
- Applicant: Realtek Semiconductor Corp.
- Applicant Address: TW Hsinchu
- Assignee: REALTEK SEMICONDUCTOR CORP.
- Current Assignee: REALTEK SEMICONDUCTOR CORP.
- Current Assignee Address: TW Hsinchu
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Priority: TW106128180A 20170818
- Main IPC: H03K17/16
- IPC: H03K17/16 ; H03K17/14

Abstract:
A switching circuit includes: a main switch array including multiple main switch elements respectively arranged on multiple main signal paths configured in a parallel connection, wherein the multiple main signal paths are coupled with a first circuit node; a main switch control circuit for controlling the multiple main switch elements; an auxiliary switch array including multiple auxiliary switch elements respectively arranged on multiple auxiliary signal paths configured in a parallel connection, wherein the multiple auxiliary signal paths are also coupled with the first circuit node; and an auxiliary switch control circuit for controlling the multiple auxiliary switch elements so as to maintain a total number of turned-on switch elements in the main switch array and the auxiliary switch array to be equal to or more than a threshold quantity.
Public/Granted literature
- US20190058467A1 SWITCHING CIRCUIT CAPABLE OF REDUCING PARASITIC CAPACITANCE VARIATION Public/Granted day:2019-02-21
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