Invention Grant
- Patent Title: Load-hit-load detection in an out-of-order processor
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Application No.: US15726563Application Date: 2017-10-06
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Publication No.: US10534616B2Publication Date: 2020-01-14
- Inventor: Christopher Gonzalez , Bryan Lloyd , Balaram Sinharoy
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Jason Sosa
- Main IPC: G06F9/312
- IPC: G06F9/312 ; G06F9/445 ; G06F9/38 ; G06F9/24 ; G06F9/48 ; G06F9/30

Abstract:
Technical solutions are described for executing one or more out-of-order instructions by a load-store unit (LSU) by detecting a load-hit-load (LHL) case based only on effective addresses (EA). An example method includes, in response to receiving a first load instruction, creating an entry in a LHL table. Further, in response to receiving a second load instruction in the load reorder queue, and in response to the predetermined number of bits from a second EA used by the second load instruction matching the predetermined number of bits from the first EA, comparing the first EA and the second EA. Further, a first thread identifier for the first load instruction is compared with a second thread identifier for the second load instruction. In response to the first EA matching the second EA, and the first thread identifier matching the second thread identifier, the method includes flushing the first load instruction.
Public/Granted literature
- US20190108035A1 LOAD-HIT-LOAD DETECTION IN AN OUT-OF-ORDER PROCESSOR Public/Granted day:2019-04-11
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