Invention Grant
- Patent Title: Methods of forming a vertical semiconductor diode using an engineered substrate
-
Application No.: US16213512Application Date: 2018-12-07
-
Publication No.: US10535547B2Publication Date: 2020-01-14
- Inventor: Vladimir Odnoblyudov , Dilip Risbud , Ozgur Aktas , Cem Basceri
- Applicant: QROMIS, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: QROMIS, Inc.
- Current Assignee: QROMIS, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Kilpatrick Townsend & Stockton LLP
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L21/683 ; H01L29/778 ; H01L29/861 ; H01L21/02 ; H01L21/28 ; H01L21/48 ; H01L29/10 ; H01L29/20 ; H01L29/205 ; H01L29/417 ; H01L29/423 ; H01L29/66 ; C30B25/18 ; C30B29/06 ; C30B29/40 ; H01L29/872 ; H01L29/40
Abstract:
A semiconductor diode includes an engineered substrate including a substantially single crystal layer, a buffer layer coupled to the substantially single crystal layer, and a semi-insulating layer coupled to the buffer layer. The semiconductor diode also includes a first N-type gallium nitride layer coupled to the semi-insulating layer and a second N-type gallium nitride layer coupled to the first N-type gallium nitride layer. The first N-type gallium nitride layer has a first doping concentration and the second N-type gallium nitride layer has a second doping concentration less than the first doping concentration. The semiconductor diode further includes a P-type gallium nitride layer coupled to the second N-type gallium nitride layer, an anode contact coupled to the P-type gallium nitride layer, and a cathode contact coupled to a portion of the first N-type gallium nitride layer.
Public/Granted literature
- US20190122916A1 VERTICAL SEMICONDUCTOR DIODE MANUFACTURED WITH AN ENGINEERED SUBSTRATE Public/Granted day:2019-04-25
Information query
IPC分类:
