A method includes forming a transistor including forming a source/drain region on a side of a dummy gate stack, forming a first Inter-Layer Dielectric (ILD) covering the source/drain region, and replacing the dummy gate stack with a replacement gate stack. The method further includes forming a second ILD over the first ILD and the replacement gate stack, and forming a lower source/drain contact plug electrically coupling to the source/drain region. The lower source/drain contact plug penetrates through both the first ILD and the second ILD. A third ILD is formed over the second ILD. A gate contact plug is formed in the second ILD and the third ILD. An upper source/drain contact plug is formed overlapping and contacting the lower source/drain contact plug. The upper source/drain contact plug penetrates through the third ILD. The upper source/drain contact plug and the gate contact plug are formed of different materials.