- Patent Title: Fabricating method of oxide layer within peripheral circuit region
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Application No.: US16012744Application Date: 2018-06-19
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Publication No.: US10535664B2Publication Date: 2020-01-14
- Inventor: Po-Chun Chen , Wei-Hsin Liu , Chia-Lung Chang , Yi-Wei Chen , Han-Yung Tsai
- Applicant: UNITED MICROELECTRONICS CORP. , Fujian Jinhua Integrated Circuit Co., Ltd.
- Applicant Address: TW Hsin-Chu CN Quanzhou, Fujian Province
- Assignee: UNITED MICROELECTRONICS CORP.,Fujian Jinhua Integrated Circuit Co., Ltd.
- Current Assignee: UNITED MICROELECTRONICS CORP.,Fujian Jinhua Integrated Circuit Co., Ltd.
- Current Assignee Address: TW Hsin-Chu CN Quanzhou, Fujian Province
- Agent Winston Hsu
- Priority: CN201810520798 20180528
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L27/108 ; H01L29/66 ; H01L21/02 ; H01L21/265 ; H01L21/266 ; H01L29/78

Abstract:
A method of changing a formation rate of silicon oxide includes providing a substrate, wherein two conductive lines are disposed on the substrate and a recess is between the conductive lines. Later, a cleaning process is performed to clean the substrate and the conductive lines using diluted hydrofluoric acid. After the cleaning process, a silicon oxide layer is formed to cover a sidewall and a bottom of the recess, wherein a formation rate of the silicon oxide layer at the bottom of the recess is greater than a formation rate of the silicon oxide layer at the sidewall of the recess.
Public/Granted literature
- US20190363093A1 FABRICATING METHOD OF OXIDE LAYER WITHIN PERIPHERAL CIRCUIT REGION Public/Granted day:2019-11-28
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