Invention Grant
- Patent Title: Stacked wafer arrangement for global shutter pixels utilizing capacitive deep trench isolations
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Application No.: US15919838Application Date: 2018-03-13
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Publication No.: US10535695B2Publication Date: 2020-01-14
- Inventor: Jeffrey M. Raynor
- Applicant: STMicroelectronics (Research & Development) Limited
- Applicant Address: GB Marlow
- Assignee: STMicroelectronics (Research & Development) Limited
- Current Assignee: STMicroelectronics (Research & Development) Limited
- Current Assignee Address: GB Marlow
- Agency: Crowe & Dunlevy
- Main IPC: H01L27/146
- IPC: H01L27/146 ; H01L27/30 ; H04N5/363 ; H04N5/378

Abstract:
Described herein is an electronic device that includes a first integrated circuit die having formed therein at least one photodiode and readout circuitry to convert charge generated by the at least one photodiode to a read voltage and to selectively output the read voltage. A second integrated circuit die is in a stacked arrangement with the first integrated circuit die and has formed therein storage circuitry to selectively transfer the read voltage to at least one storage capacitor for storage as a stored voltage and to selectively transfer the stored voltage to an output. The at least one storage capacitor is formed from a capacitive deep trench isolation. There is an interconnect between the first and second integrated circuit dies for coupling the readout circuitry to the storage circuitry.
Public/Granted literature
- US20190288023A1 STACKED WAFER ARRANGEMENT FOR GLOBAL SHUTTER PIXELS UTILIZING CAPACITIVE DEEP TRENCH ISOLATIONS Public/Granted day:2019-09-19
Information query
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