Invention Grant
- Patent Title: Scaled TFET transistor formed using nanowire with surface termination
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Application No.: US15505558Application Date: 2014-09-24
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Publication No.: US10535770B2Publication Date: 2020-01-14
- Inventor: Uygar E. Avci , Rafael Rios , Kelin J. Kuhn , Ian A. Young , Justin R. Weber
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Green, Howard & Mughal LLP
- International Application: PCT/US2014/057258 WO 20140924
- International Announcement: WO2016/048306 WO 20160331
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/78 ; H01L29/739 ; B82Y10/00 ; H01L29/16 ; H01L29/20 ; H01L29/24 ; H01L29/66

Abstract:
Described is a TFET comprising: a nanowire having doped regions for forming source and drain regions, and an un-doped region for coupling to a gate region; and a first termination material formed over the nanowire; and a second termination material formed over a section of the nanowire overlapping the gate and source regions. Described is another TFET comprising: a first section of a nanowire having doped regions for forming source and drain regions, and an undoped region for coupling to a gate region; a second section of the nanowire extending orthogonal to the first section, the second section formed next to the gate and source regions; and a termination material formed over the first and second sections of the nanowire.
Public/Granted literature
- US20170271501A1 SCALED TFET TRANSISTOR FORMED USING NANOWIRE WITH SURFACE TERMINATION Public/Granted day:2017-09-21
Information query
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