Invention Grant
- Patent Title: Image sensor having stacked imaging and digital wafers where the digital wafer has stacked capacitors and logic circuitry
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Application No.: US16127922Application Date: 2018-09-11
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Publication No.: US10536658B2Publication Date: 2020-01-14
- Inventor: Jeffrey M. Raynor
- Applicant: STMicroelectronics (Research & Development) Limited
- Applicant Address: GB Marlow
- Assignee: STMicroelectronics (Research & Development) Limited
- Current Assignee: STMicroelectronics (Research & Development) Limited
- Current Assignee Address: GB Marlow
- Agency: Crowe & Dunlevy
- Main IPC: H04N5/374
- IPC: H04N5/374 ; H01L27/146 ; H04N5/378

Abstract:
An electronic device includes a first integrated circuit die having formed therein photodiodes and readout circuitry for the photodiodes, with the readout circuitry including output pads exposed on a surface of the first integrated circuit die. A second integrated circuit die has formed therein storage capacitor structures for the photodiodes and digital circuitry for performing image processing on data stored in the storage capacitor structures, with the storage capacitor structures including input pads exposed on a surface of the second integrated circuit die. The first and second integrated circuit die are in a face to face arrangement such that the output pads of the first integrated circuit die face the input pads of the second integrated circuit die. An interconnect couples the output pads of the first integrated circuit die to the input pads of the second integrated circuit die.
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