Invention Grant
- Patent Title: Dynamic instruction latency management in SIMD machines
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Application No.: US15903393Application Date: 2018-02-23
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Publication No.: US10540260B2Publication Date: 2020-01-21
- Inventor: Travis Schluessler , Abhishek Venkatesh , Elmoustapha Ould-Ahmed-Vall , John Gierach , Tomer Bar On , Devan Burke
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Jaffery Watson Mendonsa & Hamilton LLP
- Main IPC: G06F9/44
- IPC: G06F9/44 ; G06F11/36 ; G06F9/38 ; G06T1/20
Abstract:
In one example, an apparatus comprises processing circuitry to analyze a program at compile time to determine a set of latency parameters associated with instruction sets implemented to execute the program and select a latency management technique based at least in part on the set of latency parameters associated with instruction sets implemented to execute the program. Other examples may be described and claimed.
Public/Granted literature
- US20190266069A1 Dynamic Instruction Latency Management in SIMD Machines Public/Granted day:2019-08-29
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