A method includes providing a register transfer level (RTL) description of a circuit design, providing a plurality of RTL-to-gate-level mapping details by translating the RTL description into a gate-level netlist, providing one or more input/output (I/O) variables as stimulus to simulate the RTL description of the circuit design, capturing a plurality of internal operation values from the simulated RTL description at a beginning time of a specified period of time wherein the specified period of time is less than a time period required to compete a full-scale simulation, mapping the captured internal operation values to corresponding gate-level nodes of the gate-level netlist, capturing a plurality of I/O values from the I/O variables at the beginning time of the specified period of time, and simulating the circuit design in a gate-level for the specified period of time based on the mapped internal operation values and the captured I/O values.