A stacked chip layout includes a central processing chip; and a first active circuit block over the central processing chip. The stacked chip layout further includes a second active circuit block over the first active circuit. A center of the second active circuit block is offset from a center of the first active circuit block, the second active circuit block overlaps the first active circuit block in a partial overlap area, and the second active circuit block exposes a portion of the first active circuit block. The stacked chip layout further includes a local conductive element electrically connecting the first active circuit block to the second active circuit block. The local conductive element is within the partial overlap area.