Invention Grant
- Patent Title: Memory system for restraining threshold variation to improve data reading
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Application No.: US15916538Application Date: 2018-03-09
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Publication No.: US10541030B2Publication Date: 2020-01-21
- Inventor: Masanobu Shirakawa , Marie Takada , Tsukasa Tokutomi , Yoshihisa Kojima , Kiichi Tachi
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Minato-ku
- Assignee: Toshiba Memory Corporation
- Current Assignee: Toshiba Memory Corporation
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2017-180531 20170920
- Main IPC: G11C16/04
- IPC: G11C16/04 ; G11C16/08 ; G11C16/34 ; H01L27/1157 ; G11C16/12 ; G11C16/26 ; H01L27/11582

Abstract:
According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.
Public/Granted literature
- US20190088333A1 MEMORY SYSTEM Public/Granted day:2019-03-21
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