Invention Grant
- Patent Title: Electronics package with integrated interconnect structure and method of manufacturing thereof
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Application No.: US15668468Application Date: 2017-08-03
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Publication No.: US10541153B2Publication Date: 2020-01-21
- Inventor: Christopher James Kapusta , Raymond Albert Fillion , Risto Ilkka Sakari Tuominen , Kaustubh Ravindra Nagarkar
- Applicant: General Electric Company
- Applicant Address: US NY Schenectady
- Assignee: General Electric Company
- Current Assignee: General Electric Company
- Current Assignee Address: US NY Schenectady
- Agency: Ziolkowski Patent Solutions Group, SC
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L21/56 ; H01L21/52 ; H01L23/28 ; H01L23/31
Abstract:
An electronics package includes an insulating substrate, an electrical component having a back surface coupled to a first surface of the insulating substrate, and an insulating structure surrounding at least a portion of a perimeter of the electrical component. A first wiring layer extends from the first surface of the insulating substrate and over a sloped side surface of the insulating structure to electrically couple with at least one contact pad on an active surface of the electrical component. A second wiring layer is formed on a second surface of the insulating substrate and extends through at least one via therein to electrically couple with the first wiring layer.
Public/Granted literature
- US20190043733A1 ELECTRONICS PACKAGE WITH INTEGRATED INTERCONNECT STRUCTURE AND METHOD OF MANUFACTURING THEREOF Public/Granted day:2019-02-07
Information query
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