Invention Grant
- Patent Title: 3D IC bump height metrology APC
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Application No.: US16234675Application Date: 2018-12-28
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Publication No.: US10541164B2Publication Date: 2020-01-21
- Inventor: Nai-Han Cheng , Chi-Ming Yang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: G01B11/14
- IPC: G01B11/14 ; G01B11/16 ; G01B11/24 ; H01L21/67 ; H01L21/768 ; H01L25/00 ; H01L21/66 ; H01L21/68 ; H01L23/00 ; H01L25/065

Abstract:
The present disclosure, in some embodiments, relates to a substrate metrology system. The substrate metrology system includes a substrate warpage measurement module configured to determine one or more substrate warpage parameters of a substrate by taking a plurality of separate measurements at a plurality of different positions over a substrate. The substrate has a plurality of conductive interconnect layers within a dielectric structure over a semiconductor substrate and a conductive bump disposed over the dielectric structure and configured to be coupled to an additional substrate of a multi-dimensional chip. A substrate metrology module has an optical component and is configured to measure one or more dimensions of the conductive bump. A position control element is configured to move the optical component. A feed-forward path is coupled between an output of the substrate warpage measurement module and an input of the position control element.
Public/Granted literature
- US20190139800A1 3D IC BUMP HEIGHT METROLOGY APC Public/Granted day:2019-05-09
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