Invention Grant
- Patent Title: Interconnect structure and method of forming the same
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Application No.: US15875442Application Date: 2018-01-19
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Publication No.: US10541174B2Publication Date: 2020-01-21
- Inventor: Soo Doo Chae , Jeffrey Smith , Gerrit J. Leusink , Robert D. Clark , Kai-Hung Yu
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Minato-ku
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/768 ; H01L23/522 ; H01L23/532 ; H01L21/285

Abstract:
A semiconductor device is provided. The semiconductor device can have a substrate including dielectric material. A plurality of narrow interconnect openings can be formed within said dielectric material. In addition, a plurality of wide interconnect openings can be formed within said dielectric material. The semiconductor device can include a first metal filling the narrow interconnect openings to form an interconnect structure and conformally covering a surface of the wide interconnect openings formed in the dielectric material, and a second metal formed over the first metal and encapsulated by the first metal to form another interconnect structure within the wide interconnect openings.
Public/Granted literature
- US20180211870A1 INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME Public/Granted day:2018-07-26
Information query
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