Invention Grant
- Patent Title: Wafer and wafer defect analysis method
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Application No.: US16401417Application Date: 2019-05-02
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Publication No.: US10541181B2Publication Date: 2020-01-21
- Inventor: Jae Hyeong Lee
- Applicant: SK SILTRON CO., LTD.
- Applicant Address: KR Gum-si, Gyeongsangbuk-Do
- Assignee: SK SILTRON CO., LTD.
- Current Assignee: SK SILTRON CO., LTD.
- Current Assignee Address: KR Gum-si, Gyeongsangbuk-Do
- Agency: KED & Associates, LLP
- Priority: KR10-2015-0094243 20150701
- Main IPC: H01L29/30
- IPC: H01L29/30 ; H01L21/66 ; H01L29/32 ; H01L21/324
Abstract:
A wafer defect analysis method according to one embodiment comprises the steps of: thermally treating a wafer at different temperatures; measuring an oxygen precipitate index of the thermally treated wafer; determining a characteristic temperature at which the oxygen precipitate index is maximized; and discriminating a type of defect region of the wafer depending on the determined characteristic temperature.
Public/Granted literature
- US20190267294A1 WAFER AND WAFER DEFECT ANALYSIS METHOD Public/Granted day:2019-08-29
Information query
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