Invention Grant
- Patent Title: Printed repassivation for wafer chip scale packaging
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Application No.: US16053199Application Date: 2018-08-02
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Publication No.: US10541220B1Publication Date: 2020-01-21
- Inventor: Daiki Komatsu , Makoto Shibuya , Yi Yan , Hau Nguyen , Luu Thanh Nguyen , Anindya Poddar
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Ronald O. Neerings; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L21/56 ; H01L21/78 ; H01L23/00 ; H01L23/367 ; H01L23/498 ; H01L23/495 ; H01L23/31
Abstract:
Described examples provide integrated circuits and methods, including forming a conductive seed layer at least partially above a conductive feature of a wafer, forming a conductive structure on at least a portion of the conductive seed layer, performing a printing process that forms a polymer material on a side of the wafer proximate a side of the conductive structure, curing the deposited polymer material, and attaching a solder ball structure to a side of the conductive structure.
Public/Granted literature
- US20200043878A1 PRINTED REPASSIVATION FOR WAFER CHIP SCALE PACKAGING Public/Granted day:2020-02-06
Information query
IPC分类:
