Invention Grant
- Patent Title: System on integrated chips and methods of forming same
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Application No.: US16126428Application Date: 2018-09-10
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Publication No.: US10541227B2Publication Date: 2020-01-21
- Inventor: Sung-Feng Yeh , Chen-Hua Yu , Ming-Fa Chen
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L25/065 ; H01L23/522 ; H01L23/00 ; H01L21/48 ; H01L21/56 ; H01L23/31 ; H01L25/00 ; H01L23/498

Abstract:
An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die.
Public/Granted literature
- US20190027465A1 System on Integrated Chips and Methods of Forming Same Public/Granted day:2019-01-24
Information query
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