A non-volatile memory module includes an input/output buffer coupled to first and second signal transmission paths, and control circuitry coupled to the input/output buffer, the control circuitry being configured to receive a first signal on the first signal transmission path, receive a second signal on the second signal transmission path, determine a delay between the first signal and the second signal, generate a delay mismatch value based on the determined delay, and transmit the delay mismatch value on one or more signal transmission paths coupled to the input/output buffer.