Invention Grant
- Patent Title: Method to reduce trap-induced capacitance in interconnect dielectric barrier stack
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Application No.: US16237407Application Date: 2018-12-31
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Publication No.: US10546742B2Publication Date: 2020-01-28
- Inventor: He Ren , Mehul B. Naik , Yong Cao , Yana Cheng , Weifeng Ye
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: APPLIED MATERIALS, INC.
- Current Assignee: APPLIED MATERIALS, INC.
- Current Assignee Address: US CA Santa Clara
- Agency: Patterson + Sheridan LLP
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L21/768

Abstract:
The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer.
Public/Granted literature
- US20190189433A1 METHOD TO REDUCE TRAP-INDUCED CAPACITANCE IN INTERCONNECT DIELECTRIC BARRIER STACK Public/Granted day:2019-06-20
Information query
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