Invention Grant
- Patent Title: Wafer level integration including design/co-design, structure process, equipment stress management and thermal management
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Application No.: US15272804Application Date: 2016-09-22
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Publication No.: US10546836B2Publication Date: 2020-01-28
- Inventor: Bing Dang , Li-Wen Hung , John U. Knickerbocker , Jae-Woong Nah
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Fleit Intellectual Property Law
- Agent Donna Flores
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/00 ; H01L21/02 ; H01L25/00
Abstract:
A multi-layer wafer and method of manufacturing such wafer are provided. The method includes creating under bump metallization (UMB) pads on each of the two heterogeneous wafers; applying a conductive means above the UMB pads on at least one of the two heterogeneous wafers; and low temperature bonding the two heterogeneous wafers to adhere the UMB pads together via the conductive means. At least one stress compensating polymer layer may be applied to at least one of two heterogeneous wafers. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafer having UMB pads and at least one of the heterogeneous wafers having a stress compensating polymer layer and a conductive means applied above the UMB pads on at least one of the two heterogeneous wafers. The two heterogeneous wafers low temperature bonded together to adhere the UMB pads together via the conductive means.
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