- Patent Title: Vertical transistor transmission gate with adjacent NFET and PFET
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Application No.: US15434753Application Date: 2017-02-16
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Publication No.: US10546857B2Publication Date: 2020-01-28
- Inventor: Karthik Balakrishnan , Kangguo Cheng , Pouya Hashemi , Alexander Reznicek
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent L. Jeffrey Kelly, Esq.
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L29/78 ; H01L29/06 ; H01L29/10 ; H01L21/8238 ; H01L29/66 ; H01L21/762

Abstract:
A complementary metal oxide semiconductor (CMOS) vertical transistor structure with closely spaced p-type and n-type vertical field effect transistors (FETs) is provided. After forming a dielectric material portion contacting a proximal sidewall of a first semiconductor fin for formation of a p-type vertical FET and a proximal sidewall of a second semiconductor fin for formation of an n-type vertical FET, a first gate structure is formed contacting a distal sidewall of the first semiconductor fin, and a second gate structure is formed contacting a distal sidewall of the second semiconductor fin. Because no gate structures are formed between the first and second semiconductor fins, the p-type vertical FET is spaced from the n-type FET only by the dielectric material portion.
Public/Granted literature
- US20180233501A1 VERTICAL TRANSISTOR TRANSMISSION GATE WITH ADJACENT NFET AND PFET Public/Granted day:2018-08-16
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