Invention Grant
- Patent Title: Methods of forming memory and methods of forming vertically-stacked structures
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Application No.: US13759707Application Date: 2013-02-05
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Publication No.: US10546998B2Publication Date: 2020-01-28
- Inventor: John D. Hopkins
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L45/00
- IPC: H01L45/00 ; H01L27/24

Abstract:
Some embodiments include constructions having electrically conductive bitlines within a stack of alternating electrically conductive wordline levels and electrically insulative levels. Cavities extend into the electrically conductive wordline levels, and phase change material is within the cavities. Some embodiments include methods of forming memory. An opening is formed through a stack of alternating electrically conductive levels and electrically insulative levels. Cavities are extended into the electrically conductive levels along the opening. Phase change material is formed within the cavities, and incorporated into vertically-stacked memory cells. An electrically conductive interconnect is formed within the opening, and is electrically coupled with a plurality of the vertically-stacked memory cells.
Public/Granted literature
- US20140217349A1 Methods of Forming Memory and Methods of Forming Vertically-Stacked Structures Public/Granted day:2014-08-07
Information query
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