Disclosed is a clock data recovery (CDR) device including a master lane circuit and a plurality of slave lane circuits. The master lane circuit includes: a clock multiplication unit including a phase frequency detector (PFD), a charge pump (CP), a voltage-controlled oscillator (VCO), and a loop divider; a master lane sampling circuit; a master lane phase detector (PD); and a master lane multiplexer coupled between the master lane PD and the CP and between the PFD and the CP. Each slave lane circuit includes: a slave lane sampling circuit (SLS); a slave lane PD; a slave lane digital loop filter; a phase rotator (PR); and a slave lane multiplexer coupled between the VCO and the SLS and between the PR and the SLS, in which the master lane multiplexer and the slave lane multiplexers are configured to have the CDR device operate in one of multiple modes.