Invention Grant
- Patent Title: Corrupt logical block addressing recovery scheme
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Application No.: US15782119Application Date: 2017-10-12
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Publication No.: US10552243B2Publication Date: 2020-02-04
- Inventor: Roman A. Pletka , Timothy J. Fisher , Robert E. Galbraith , Kevin E. Sallese , Christopher M. Dennett
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent David B. Woycechowsky
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/07 ; G06F11/10 ; G11B20/18

Abstract:
Technology for handling page size mismatches when DPL-CLR is performed at multiple levels of a data storage system (for example, RAID level and flash card level). A “corrective DPL” corrects only a portion of the data that would make up a page at the level at which the data is stored (that is, the “initial DPL level”), and, after that, a partially corrected page of data is formed and stored in data storage, with the partially corrected page: (i) having a page size characteristic of the initial DPL; (ii) including the part of the data corrected by the corrective DPL; and (iii) further including other data. In some embodiments, the other data has a pattern that indicates that it is invalid, erroneous data, such that an error message will be returned if this portion of the data is attempted to be read.
Public/Granted literature
- US20190114217A1 CORRUPT LOGICAL BLOCK ADDRESSING RECOVERY SCHEME Public/Granted day:2019-04-18
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