In general, the present embodiments are directed to designing an electronic system such as an IC, and more particularly to techniques for analyzing a design for potential ESD instance failures. Embodiments allow for efficiently determining a potential ESD violation or non-violation status for a large number of instances, such as all the instances in a full chip design, by performing effective resistance analyses between all the instances and all the bumps and ESD protection devices in the design. These and other embodiments further allow for more detailed effective resistance analyses to be performed for potential failing instances.