A phase change memory device may include a cross point array and a sensing circuit block. The cross point array may include a plurality of word lines, a plurality of bit lines and phase change memory cells. The word lines and the bit lines may intersect each other. The phase change memory cells are positioned at intersection points between the word lines and the bit lines. The sensing circuit block reads data in the phase change memory cells. The sensing circuit block may include a first sensing unit and a second sensing unit. The first sensing unit senses the data using a first voltage. The second sensing unit senses the data using a second voltage, which may be higher than a threshold voltage of the phase change memory cell, when the data in the phase change memory cell read by the first sensing unit is determined to be abnormal.