A memory device includes a memory cell array including a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines; a read/write circuit including a plurality of page buffers coupled to the plurality of bit lines; a power supply circuit suitable for generating voltages to be applied to the memory cell array and the read/write circuit; and a control circuit suitable for receiving a read command and an address signal from an external device, and controlling the memory cell array, the read/write circuit and the power supply circuit based on the read command and the address signal.