Invention Grant
- Patent Title: Cut last self-aligned litho-etch patterning
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Application No.: US15696498Application Date: 2017-09-06
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Publication No.: US10553431B2Publication Date: 2020-02-04
- Inventor: Kuan-Wei Huang , Chia-Ying Lee , Ming-Chung Liang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L21/033
- IPC: H01L21/033 ; H01L27/11

Abstract:
The present disclosure relates to a method of performing a semiconductor fabrication process. The method may be performed by forming a spacer material having vertically extending segments along sidewalls of a masking layer and a horizontally extending segment connecting the vertically extending segments. A cut material is formed over a part of the horizontally extending segment, and the horizontally extending segment of the spacer material not covered by the cut material is removed. A layer under the masking layer is patterned according to the masking layer and the spacer material.
Public/Granted literature
- US20170365472A1 CUT LAST SELF-ALIGNED LITHO-ETCH PATTERNING Public/Granted day:2017-12-21
Information query
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