Invention Grant
- Patent Title: Semiconductor device with reduced via resistance
-
Application No.: US15897526Application Date: 2018-02-15
-
Publication No.: US10553483B2Publication Date: 2020-02-04
- Inventor: Conal E. Murray , Chih-Chao Yang
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Isaac J. Gooshaw
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40 ; H01L21/768 ; H01L23/532 ; H01L23/522 ; H01L23/528 ; C23F4/00 ; C23F1/44

Abstract:
A method of fabricating a semiconductor interconnect structure by providing a semiconductor structure with a dielectric layer with and an embedded electrically conductive structure. A dielectric capping layer and a metal capping layer separating a second dielectric layer located above the first dielectric layer. The segment of metal capping layer covers at least a portion of a top surface of the first electrically conductive structure. Exposing parts of both the first electrically conductive structure and the dielectric capping layer by forming an opening in the second dielectric layer and the metal capping layer. Forming a second electrically conductive structure in the opening, such that (i) the second electrically conductive structure is located over part of the dielectric capping layer, and (ii) the second electrically conductive structure is in electrical contact with the first electrically conductive structure.
Public/Granted literature
- US20180174903A1 SEMICONDUCTOR DEVICE WITH REDUCED VIA RESISTANCE Public/Granted day:2018-06-21
Information query
IPC分类: