Invention Grant
- Patent Title: Selective NFET/PFET recess of source/drain regions
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Application No.: US15966858Application Date: 2018-04-30
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Publication No.: US10553492B2Publication Date: 2020-02-04
- Inventor: Yun-Min Chang , Chien-An Chen , Guan-Ren Wang , Peng Wang , Huang-Ming Chen , Huan-Just Lin
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L29/66 ; H01L21/311 ; H01L21/768 ; H01L29/78 ; H01L27/088

Abstract:
A method includes forming an inter-layer dielectric over a first source/drain region and a second source/drain region. The first source/drain region and the second source/drain region are of n-type and p-type, respectively. The inter-layer dielectric is etched to form a first contact opening and a second contact opening, with the first source/drain region and the second source/drain region exposed to the first contact opening and the second contact opening, respectively. A process gas is used to etch back the first source/drain region and the second source/drain region simultaneously, and a first etching rate of the first source/drain region is higher than a second etching rate of the second source/drain region. A first silicide region and a second silicide region are formed on the first source/drain region and the second source/drain region, respectively.
Public/Granted literature
- US20190333820A1 SELECTIVE NFET/PFET RECESS OF SOURCE/DRAIN REGIONS Public/Granted day:2019-10-31
Information query
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