Invention Grant
- Patent Title: Stacked semiconductor apparatus being electrically connected through through-via and monitoring method
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Application No.: US16175319Application Date: 2018-10-30
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Publication No.: US10553510B2Publication Date: 2020-02-04
- Inventor: Sang Ho Lee
- Applicant: SK hynix Inc.
- Applicant Address: KR Icheon-si, Gyeonggi-do
- Assignee: SK hynix Inc.
- Current Assignee: SK hynix Inc.
- Current Assignee Address: KR Icheon-si, Gyeonggi-do
- Agency: William Park & Associates Ltd.
- Priority: KR10-2014-0069442 20140609
- Main IPC: H01L21/66
- IPC: H01L21/66 ; H01L25/065 ; G01R31/26 ; G01R31/28 ; H03K5/159 ; H01L23/00 ; H01L23/48

Abstract:
A semiconductor apparatus includes a plurality of stacked chips. Each of the plurality of stacked chips includes a delay chain. Each of the plurality of stacked chips comprises a plurality of Through-Vias, wherein one of the plurality of Through-Vias formed in a first one of the plurality of stacked chips and electrically coupled to a predetermined location of a first delay chain on the first one of the plurality of stacked chips and one of the plurality of Through-Vias formed in a neighboring one of the plurality of stacked chips and electrically coupled to a predetermined location of a delay chain on the neighboring one of the plurality of stacked chips are configured to electrically couple the first one of the plurality of stacked chips to the neighboring one of the plurality of stacked chips. A signal transmitted from a first one of the plurality of stacked chips generates a feedback signal to the first one of the plurality of stacked chips through one or more of the plurality of Through-Vias.
Public/Granted literature
- US20190067136A1 STACKED SEMICONDUCTOR APPARATUS BEING ELECTRICALLY CONNECTED THROUGH THROUGH-VIA AND MONITORING METHOD Public/Granted day:2019-02-28
Information query
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