- Patent Title: Boundary region for high-k-metal-gate(HKMG) integration technology
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Application No.: US15688276Application Date: 2017-08-28
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Publication No.: US10553583B2Publication Date: 2020-02-04
- Inventor: Yi-Huan Chen , Chien-Chih Chou , Kong-Beng Thei
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L29/10 ; H01L29/66 ; H01L21/8238 ; H01L21/84 ; H01L29/06 ; H01L29/423

Abstract:
The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region, and a method of formation. In some embodiments, the integrated circuit comprises a first gate boundary dielectric layer disposed over a substrate in the low voltage region. A second gate boundary dielectric layer is disposed over the substrate in the high voltage region having a thickness greater than that of the first boundary dielectric layer. The first boundary dielectric layer meets the second boundary dielectric layer at the boundary region. A first polysilicon component is disposed within the boundary region over the first boundary dielectric layer and the second gate boundary layer. A second polysilicon component is disposed within the boundary region over the first polysilicon component. A hard mask component is disposed over the first polysilicon component and laterally neighbored to the second polysilicon component.
Public/Granted literature
- US20190067282A1 BOUNDARY REGION FOR HKMG INTEGRATION TECHNOLOGY Public/Granted day:2019-02-28
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