Invention Grant
- Patent Title: Memory cell including a plurality of wells
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Application No.: US16231854Application Date: 2018-12-24
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Publication No.: US10553597B2Publication Date: 2020-02-04
- Inventor: Shih-Hsien Chen , Liang-Tai Kuo , Hau-Yan Lu , Chun-Yao Ko
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Hauptman Ham, LLP
- Main IPC: H01L27/11526
- IPC: H01L27/11526 ; H01L29/49 ; H01L27/02 ; H01L23/528 ; H01L29/10 ; H01L29/66 ; H01L27/11558 ; H01L27/11521 ; H01L29/94
Abstract:
A memory cell includes a first transistor coupled to a source line, wherein the first transistor is in a first well. The memory cell further includes a second transistor coupled to the first transistor and a bit line, wherein the second transistor is in the first well. The memory cell further includes a first capacitor coupled to a word line and the second transistor, wherein the first capacitor is in a second well. The memory cell further includes a second capacitor coupled to the second transistor and an erase gate, wherein the second capacitor is in the second well. In some embodiments, the first well contacts the second well on a first side of the first well.
Public/Granted literature
- US20190131312A1 MEMORY DEVICE AND MEMORY CELL Public/Granted day:2019-05-02
Information query
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