Invention Grant
- Patent Title: Circuit and layout for resistive random-access memory arrays having two bit lines per column
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Application No.: US16155083Application Date: 2018-10-09
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Publication No.: US10553643B2Publication Date: 2020-02-04
- Inventor: John L McCollum
- Applicant: Microsemi SoC Corp.
- Applicant Address: US CA San Jose
- Assignee: Microsemi SoC Corp.
- Current Assignee: Microsemi SoC Corp.
- Current Assignee Address: US CA San Jose
- Agency: Glass and Associates
- Agent Kenneth D'Alessandro; Kenneth Glass
- Main IPC: H01L27/24
- IPC: H01L27/24 ; G11C13/00 ; H01L45/00 ; H01L29/08 ; H01L29/78
Abstract:
A layout is presented for a ReRAM memory cell array including rows and columns of ReRAM cells, each ReRAM cell is in a row and column of ReRAM cells. Each ReRAM cell includes a ReRAM device. A first transistor is coupled between the ReRAM device and a first bit line associated with the column containing the ReRAM cell. The first transistor has a gate coupled to a first word line associated with the row containing the ReRAM cell. A second transistor is coupled between the ReRAM device and a second bit line associated with the column containing the ReRAM cell. The second transistor has a gate coupled to a second word line associated with the row containing the ReRAM cell.
Public/Granted literature
- US20200006429A1 CIRCUIT AND LAYOUT FOR RESISTIVE RANDOM-ACCESS MEMORY ARRAYS HAVING TWO BIT LINES PER COLUMN Public/Granted day:2020-01-02
Information query
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