- Patent Title: Method for Modelica-based system fault analysis at the design stage
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Application No.: US15392196Application Date: 2016-12-28
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Publication No.: US10558766B2Publication Date: 2020-02-11
- Inventor: Bhaskar Saha , Tomonori Honda , Ion Matei , Daniel G. Bobrow , Johan Dekleer , William C. Janssen , Tolga Kurtoglu
- Applicant: Palo Alto Research Center Incorporated
- Applicant Address: US CA Palo Alto
- Assignee: Palo Alto Research Center Incorporated
- Current Assignee: Palo Alto Research Center Incorporated
- Current Assignee Address: US CA Palo Alto
- Agency: Fay Sharpe LLP
- Main IPC: G06F11/36
- IPC: G06F11/36 ; G06F17/50 ; G06F11/00 ; G06F17/18 ; G05B23/02 ; G06N7/00 ; G06N7/02 ; G06N20/00
Abstract:
A new and/or improved method, apparatus and/or system is disclosed which aids in extending correct behavioral models to include fault modes and in fault mode analysis of components and/or systems in simulated model environments, including, e.g., FMEA and FMECA and diagnostic fault tree generation.
Public/Granted literature
- US20170193143A1 METHOD FOR MODELICA-BASED SYSTEM FAULT ANALYSIS AT THE DESIGN STAGE Public/Granted day:2017-07-06
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