- Patent Title: Semiconductor process for improving loading effect in planarization
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Application No.: US16152366Application Date: 2018-10-04
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Publication No.: US10559473B2Publication Date: 2020-02-11
- Inventor: Feng-Yi Chang , Fu-Che Lee
- Applicant: UNITED MICROELECTRONICS CORP. , Fujian Jinhua Integrated Circuit Co., Ltd.
- Applicant Address: TW Hsin-Chu CN Quanzhou, Fujian Province
- Assignee: UNITED MICROELECTRONICS CORP.,Fujian Jinhua Integrated Circuit Co., Ltd.
- Current Assignee: UNITED MICROELECTRONICS CORP.,Fujian Jinhua Integrated Circuit Co., Ltd.
- Current Assignee Address: TW Hsin-Chu CN Quanzhou, Fujian Province
- Agent Winston Hsu
- Priority: CN201711163834 20171121
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L21/3105 ; H01L21/768 ; H01L27/108

Abstract:
A semiconductor process for improving loading effects in planarization is provided including steps of forming multiple first protruding patterns on a first region and a second region of a substrate, wherein the pattern density of the first protruding patterns in the first region is larger than the one in the second region, forming a first dielectric layer on the substrate and the first protruding patterns, wherein the first dielectric layer includes multiple second protruding patterns corresponding to the first protruding patterns below, forming a second dielectric layer on the first dielectric layer, performing a first planarization process to remove parts of the second dielectric layer, so that the top surface of the second protruding patterns are exposed, performing an etch process to remove the second protruding patterns of the first dielectric layer, removing the remaining second dielectric layer, and performing another planarization process to the first dielectric layer.
Public/Granted literature
- US20190157097A1 SEMICONDUCTOR PROCESS FOR IMPROVING LOADING EFFECT IN PLANARIZATION Public/Granted day:2019-05-23
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