Invention Grant
- Patent Title: Method of manufacturing a semiconductor device with wider sidewall spacer for a high voltage MISFET
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Application No.: US15950688Application Date: 2018-04-11
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Publication No.: US10559500B2Publication Date: 2020-02-11
- Inventor: Koji Maekawa , Tatsuyoshi Mihara
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Young & Thompson
- Priority: JP2012-223643 20121005
- Main IPC: H01L21/82
- IPC: H01L21/82 ; H01L29/66 ; H01L21/8234 ; H01L21/265 ; H01L21/266 ; H01L21/311 ; H01L29/06 ; H01L29/36

Abstract:
An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The another insulating film is etched back to form sidewall spacers over side surfaces of the insulating film. Then, the sidewall spacers over the side surfaces of the insulating films corresponding to the sidewalls of the first and second gate electrodes are removed to leave the sidewall spacers over the side surfaces of the insulating film corresponding to the sidewalls of the third gate electrode. Then, the sidewall spacers and the insulating films are etched back, so that the sidewall spacers are formed of the insulating film over the sidewalls of the first, second, and third gate electrodes.
Public/Granted literature
- US20180233414A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH WIDER SIDEWALL SPACER FOR A HIGH VOLTAGE MISFET Public/Granted day:2018-08-16
Information query
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